1 / 3 www.asb.co.kr june 2010 p lerow tm aln50 - 1001at internally matched lna module parameter unit specifications min typ max min typ max min typ max frequency range mhz 50 ~ 300 300 ~ 600 600 ~ 1000 gain db 15 16 15 16 14.5 15.5 gain flatness db ? 0.2 ? 0.25 ? 0.1 ? 0.15 ? 0.35 ? 0.4 noise figure db 2.35 2.40 2.40 2.45 2.50 2.55 output ip3 (1) dbm 40 41 40 41 38 39 s11 / s22 (2) db - 11 / - 13 - 11 / - 13 - 10 / - 10 output p1db dbm 19 20 20 21 20 21 switching time (3) sec - supply current ma 100 (typ) 120 (max) supply voltage v 5 impedance ? 50 max. rf input power dbm c.w 23 (before fail) package type & size mm surface mount type, 10wx10lx3.8h operating temperature is - 40 ? c to +85 ? c. 1) oip3 is measured with two tones at an output power of 5 dbm / tone separated by 1 mhz . 2) s11, s22 (max) is the worst value within the frequency band. 3) switching time means the time that takes for output power to get stabilized to its final level after switching dc voltage from 0 v to v s . pin number function 2 rf in 5 rf out 6 +vcc other s ground (recommended footprint) the plerow tm aln - series is the compactly designed surface - mount module for the use of the lna with or without the following gain blocks i n the infrastructure equipment of the mobile wireless (cdma, gsm, pcs, phs, wcdma, dmb, wlan, wibro, wimax), gps, satellite commun i- cation terminals and so on. it has an exceptional performance of low noise figure, high gain, high oip3, and low bias current . the stability factor is always kept more than unity over the application band in order to ensure its unconditionally stable implementation to the application system environment. the surface - mount module package including the completed matching circuit an d other components necessary just in case allows very simple and convenient implementation onto the system board in mass production level. feature s s 21 = 16.5 db@50 mhz = 15.5 db@1000 mhz 2.5 db nf(max) over frequency unconditionally s table single 5v supply high oip3@low current specifications note: 1. the number and size of ground via holes in a circuit board is critical for thermal rf grounding consider a tions. 2. w e recommend that the ground via holes be placed on the bottom of all ground pins for better rf and thermal performance, as shown in the dra w ing at the left side. description aln50 - 1001at asb inc. (top view) (bottom view) ? 0.4 plated thru holes to ground plane plerow (side view) solder s tencil area c o u pl er website: www.asb.co.kr e - mail: sales@asb.co.kr tel: (82) 42 - 528 - 722 3 f ax : (82) 42 - 528 - 7222 more inform a tion c o u pl er c o u pl er c o u pl er c o u pl er 1 - stage single type typ.@t = 25 ? c, v s = 5 v, freq. = 50~1000 mhz, z o.sys = 50 ohms
2 / 3 www.asb.co.kr june 2010 p lerow tm aln50 - 1001at internally matched lna module s - param e ters noise figure oip3 p1db 50~1000 mhz +5 v typical performance (measured) s - parameters & k fa c tor
3 / 3 www.asb.co.kr june 2010 p lerow tm aln50 - 1001at internally matched lna module 1) the tantal or mlc (multi layer ceramic) capacitor is optional and for bypassing the ac noise introduced from the dc supply. the capacitance value may be determined by customer s dc supply status . the c a- pacitor should be placed as close as possible to v s pin and be connected directly to the ground plane for the best electrical performance . 2) dc blocking capacitors are always necessarily placed at the input and output port for allowing only the rf signal to pass and blocking the dc component in the signal. the dc blocking capacitors are inclu d- ed inside the aln module. therefore, c1 & c2 capacitors may not be necessary, but can be added just in case tha t the customer wants. the value of c1 & c2 is determined by considering the application fr e- quency. application circuit recommended soldering reflow process 20~40 sec 260 ? c 200 ? c 150 ? c 60~180 sec ramp - up (3 ? c/sec) ramp - down (6 ? c/sec) in out vs size 25x25 mm (for aln - at, bt, t series C 10x10 mm) + - aln out in c1 c2 v s tantal or mlc (multi layer c e ramic) c a pacitor evaluation board layout
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